1. Field of the Invention
The present invention relates to a method of fabricating integrated electronic circuits, and in particular to the production of complex structures intended to constitute parts of electronic components on the surface of a semiconductor substrate.
2. Description of Related Art
The production of electronic components on the surface of a semiconductor substrate results in general from a complex process which is subject to constraints of various types. Such constraints relate, for example, to the arrangement of the various components, or parts of components, with respect to one another, in order to allow these components to operate in the desired manner. Other constraints, of a geometrical nature, result from the technological trend pertaining to this type of component towards ever higher levels of integration. This trend necessitates the design of more compact arrangements of components, which cannot be achieved by standard fabrication processes for integrated circuits. Yet other constraints may be of a mechanical nature, associated with the deformation liable to occur when the components are heated.
Moreover, when several levels of components or parts of components are superposed on top of the surface of a substrate, the lower levels (those closest to the surface of the substrate) are generally produced first, before the upper levels (those furthest from the surface of the substrate). The reason for this order of production is that it is expedient to be able to have access to each level of the components, during its production, via a free face of the component during production, in general the face on the opposite side to the substrate. However, certain materials incorporated into upper levels may have to be subjected in situ to heat treatments at high temperature, whereas materials incorporated into lower levels would be degraded by such heat treatments.
In practice, a compromise must often be accepted between certain characteristics of the final components and constraints such as those mentioned above.
It is known to produce components or parts of components on a first substrate and then to transfer them onto the surface of a second substrate. To do this, an initial structure corresponding to parts of components is produced on a surface of the first substrate. This first substrate is then inverted and applied against a surface of the second substrate via the initial structure. After the two substrates have been bonded together, the first substrate is removed, leaving at least part of the initial structure on the second substrate. The forming of electronic components can then be continued with the production of an additional structure on top of the initial structure portion that was transferred from the first substrate to the second.
The process of bonding the first substrate to the second substrate, by bringing a portion of the initial structure into contact with a portion of the surface of the second substrate, is known. Such a process is called molecular bonding, or wafer bonding. The surface portions of the initial structure and of the second substrate which are brought into contact with one another in such a process are usually silicon or silica portions, which are able to exhibit good adhesion between themselves when they contain no trace of foreign elements.
Removal of the first substrate, which occurs after the wafer bonding step, is carried out so as to leave at least part of the initial structure on the second substrate. This removal may be achieved by various known methods. In particular, the first substrate may be removed by polishing and/or by plasma etching. In other words, the two steps—wafer bonding and removal of the first substrate—allow the initial structure to be transferred onto the second substrate after the initial structure has been produced on the first substrate.
Such a process makes it possible to transfer, onto the surface of the second substrate, first materials that have undergone beforehand a heat treatment at high temperature, on top of second materials that would degrade at such a temperature. For this purpose, the heat treatment is applied to the first materials while they are supported by the first substrate, during production of the initial structure, and while the materials liable to be degraded have not yet been covered by the initial structure.
Such a process also makes it possible to provide, within the arrangement of the components or parts of components, volumes left empty of material, which affect the electronic behavior of the components.
One drawback of these types of methods which proceed by transferring an initial structure between two substrates appears during the continuation of the production of the structure on top of the initial structure portion that is transferred. This is because there is a need for a step of alignment between the second substrate supporting the initial structure portion transferred and a tool intended to produce the aforementioned additional structure. In practice, this step often involves positioning a photolithography mask in relation to the initial structure portion. However, this mask positioning step is complex and often requires several adjustments in order to obtain sufficient alignment precision.
Furthermore, the high levels of integration currently sought, corresponding for example to 0.12 micron or 0.10 micron technologies, or yet even finer technologies, appear to be incompatible with an intervening positioning step while certain of the components are only partly produced. This is because the alignment uncertainty currently obtained is on the order of, or even greater than, the dimensions of certain parts of components included in the initial structure portion that is transferred between the two substrates. As an example, the most precise methods currently used to align a photomask with respect to a substrate have a residual uncertainty of 60 nanometers. Even if this residual uncertainty were to be reduced, for example down to 45 nanometers, it would remain too great for already envisaged technologies for fabricating transistors having gates 30 nanometers in width.